Storage circuit

ABSTRACT

A plurality of two-input logic gates such as OR gates supplying their outputs to a three-input logic gate such as an AND gate and including a feedback connection from the three-input gate to all but one of the two-input gates. A control signal is applied to the two-input gate not receiving feedback and the complement of this control signal is applied to one of the other two-input gates. An information signal is applied to the two-input gate not receiving feedback and to a two-input gate not receiving the complement of the control signal.

United States Patent [72] inventors Jeffry Hugh Beinart Haddonfield; Daniel Hampel, Westfield, both of, N .J {211 App]. No. 840,761 [22] Filed July 10, 1969 [45] Patented Aug. 10, 1971 [73] Assignee RCA Corporation [54] STORAGE CIRCUIT 3 Claims, 4 Drawing Figs.

[52] U.S.Cl 340/173 R, 307/203. 307/221, 340/173 FF [51] lnt.Cl .rG1lcl1/40, 61 1c 19/00 [50] Field of Search 307/203, 215, 221, 291,292; 340/173 [56 1 References Cited UNITED STATES PATENTS 3,145,342 8/1964 Hill 307/215 X 3,264,567 8/1966 Prieto... 307/215 X 3,467,839 9/1969 Miller 307/215 X OTHER REFERENCES IBM Technical Disclosure Bulletin, CTRL Latch" Flynn, Vol. 1, No.6, 4/59 p- 20; 307-- 215.

IBM Technical Disclosure Bulletin, Minimal Sixteen Step Clock by Brown, Vol. 5, No. 11, 3/63 page 52,53; 307- 215 Maley et all; The Logic Design Of Transistor Digital Computers," Englewood Cliffs: Prentice-Hall, 1963, pages 259 260 Primary Examiner-Stanley M. Urynowicz, Jr. Attorney-H. Christoffersen STORAGE CIRCUIT The invention of the present application was made in the course of a contract withthe Department of the Air Force.

BACKGROUND OF THE INVENTION Storage circuits such as flip-flops are widely used in such digital circuits as registers, counters, memories and other computer circuits. The object of the present invention is to provide a new storage circuit which is relatively simple and inexpensive and which readily can be integrated.

SUMMARY OF THE INVENTION A plurality of input logic gates applying their outputs'to an output logic gate and all but one of which receive a feedback signal form the output logic gate. A control signal and its complement may be applied respectively to two of the input gates in such a way that for one value of the control signal, the circuit is insensitive to new information applied to the circuit and for another value of control signal, an information signal applied to a number of the input gates is gated into and'stored in the circuit.

BRIEF DESCRIPTION OF THE DRAWING FIG. 1 is a block diagram of one embodiment of the present invention;

FIG. 2 is a block diagram of another embodiment of the present invention;

FIG. 3 is a block diagram of a shift register employing the circuit of FIG. 1 and FIG. 2; and

FIG. 4 is a schematic diagram to indicate how the circuit of FIG. 1 may be implemented.

DETAILED DESCRIPTION The circuit of. FIG. 1 Includes three OR gates l0, l2 and 14 and a logical product gate 16, known as an AND gate. The OR,

gates are connected at their output terminals to the threeinput terminals to the AND gate 16. The AND gate is connectedat its output terminal, via feedbacklines l8and20, to the two ORgates l and 14, respectively; A control signal Tis applied to OR gate 10 andits complement Tis applied to OR gate 12 An information signal X is applied to OR gates 12 and I4. The AND gate 16 has a n ormal output Y and also may have a complemented output Y. For purposes of the presgnt discussion, it may be assumed that a complemented signal Yis obtained by aninverter stage within AND gate 16; v

In the operation of the circuit ofFlG. 1, if T=0 and T=l the circuit continues to-store the signal Y and is insensitive to X.

For example,if Y=0, since T=0 the output of OR gate 10 also is a 0 and this disables AND gate 16. Therefore AND'gate l6 continues to produce an output Y=0, regardless of the value of X. If, under the same conditions, Y=0, then the output of OR gate 10 is l, the'output' of OR gate 12 is 1 (since.T=l) and the output of OR gate 14 also is 1 (since Y=l Thus,.the three inputs to AND gate 16 all have the value I andregardlessof the value of X, Y continues to'-h ave a value representing a 1. Summarizing, when T=0 and T=l then Y=Y regardless of the value of X.

To gate a siggal into the storage circuit of- FIG. I, Tis made equal to l and Tto 0. When T=l OR gate 10 produces an output representing a l regardless of the value of Y. If now X=l, then OR gates 12 and l4 bothproduce an outputrepresenting a l, regardless of the value I. Therefore, when T=l and X=l, the three inputs to AND gate 16 represent a l and Y becomes equal to I. In similar fashion, when X=0 then the output of OR gate 12 becomes 0 (as T=0) regardless of the. previous value of Y. The output representing 0 from OR gate 12 disables AND gate 16 and its output I becomesequal to 0 regardless of itsprevious value.

The embodiment of the invention shown in FIG. 2 is made up of all identical gates, namely NAN D gates. A NAND gate implements the Boolean equation C=AB=A+B.

In the circuit of FIG. 2, the three NAND gates 50, 52 and 54 are connected to the NAND gate 56. There is a feedback connection from the output of nand gate 56 to NAND gates 50 and 54, respectively. A control signal T is applied to NAND I gate 50 and its complement T is applied to NAND gate 52.

anoutput Y=0. If Y=l, then NAND gate 50 produces an out-- put indicate of 0 since both T and Y=l. Therefore, NAND gate 56 produces an output representing a l regardless of the value of X.

When T=0 and T=l then X, the information signal, is gated to the circuit. For example, if X=l then as T is also equal to l,

NAND'gate 52 produces a 0 output. This forces NAND gate 56 to produce an output Y=l. If X=0, then NAND gates .52

and 54 both produce outputs'equal to As T alsoequals 0, NAND gate 50 also produces an output equal to l. The three 1 inputs to NAND gate 56 cause to to produce an output equal to Y=0. v

For the sake of completeness, NAND gate 56 is shown also to produce an output gidicative of 7. It will-be clear to those skilled'in the'art' that Y fungtjgn produced by nand gate 56 is the AND function as 7B =Z+=AB. In similar fashion, in the circuit of FIG, 1, the Yproduced by AND gate 16 is the NAND function. Thus, gates 56' and 16 may have the same structure.v

The shift register of FIG. 3illustrates one of the many uses for. the: circuits of FIGS. 1 and 2. Each'stage consists of two circuits'such: as shown in-FIG. 1 or 2. For example, the most significant stage consists of circuits 20 and 20a. The stage of nextsignificance-consists of circuits 22 and-22a and so on. The shift? line" is connect e dto the 7 terminal of the first circuit of each stage'and the Tterminal of the segond circuit of each stage. The shift lineis connected to the Tterminal of the first circuit of each stage and the Tterminal of the second circuit of each stage.

ln.the operation-of the shift register of FIG. 3 a uming use of the FIG. 1 circuit, to start with shift=l and shift=0. (If the FIG. 2 circuit is usedin the shiftregister, the starting condition is shift=0, shi f t=l-, but in other respects the operationis identical.) Under the set of conditions, the information signal present at terinirial24 is gatedinto the first circuit 20 in the manner. already explained in connection with FIG. 1. The second circuit, 204, whose information input terminal X is connectedto the output signal lead Y of the first circuit 20 is insensitive to the value of Y.

The next halfcycle, the values of'shift andmreverse, that is; shift becomes equal to 0 and m to 1. Now, the first circuit 20 becomes insensitiveto any new information signal which maybe present at terminal 24 and'the signal Y,, stored in the first circuit'ZO-is gated into the second circuit 200 of the first stage. This completesone shift cycle. During the first half of the cycle, new information if gated into the first circuit of the first stage andduring the next half cycle, the first circuit if made insensitive to new information and the information stored in the first circuit is shifted into the second circuit.

By repeating-the cycle above. information is shifted from stage-to stage" and new information is entered into the first stage in the same manner as discussed above. While only four circuits are shown in FIG. 3, these four circuits representing two stages of a shift register, it is to be understood, of course, that the shift register may have any length'desired.

A particularly attractive way of implementing the circuit of FIG. 1 makes use of a circuit based on a threshold logic gate described in R0. Winder, Threshold Logic Will Cut Costs Especially with Boost from LSI", Electronics, May 27, I968, pages94-l03. The circuit shown on page 102 for example, may be modified in the manner shown in FIG. 4 to provide OR gate inputs. In the circuit shown on page 102, when a signal A represents a 1, current is steered through the transistor, corresponding to 32 of FIG. 4, into one path and when it represents a 0, current is steered through the other transistor, corresponding to transistor 30 in FIG. 4, to the other path. The modification required to implement the OR function for each input is shown in FIG. 4 of the present application. Each transistor such as 32 has in shunt with its emitter-to-collector path the emitter-to-collector path of a second similar transistor 34. Now, if either Al (which in the present instance may be an input such as X) or 12 (which in the present instance may be an input such as T) represents a 1, one of the transistors 32 and 34 will conduct and a current representing 1 will flow in the collector circuit of either A I or A2.

FIG. 4 shows only one of the OR gates which is necessary in the present circuit. The complete circuit includes three sets of transistors such as 32, 34 and 30 providing three two-input OR gates for the circuit of the article. Thus, rather than inputs, A, B, C there are inputs (A,+A (B,+B and (C +C In addition, the threshold of the gate is set to the value of three in the use contemplated in the present invention. The remaining sets of input transistors (receiving inputs D...N) either are eliminated or the inputs D...N are all made to carry a constant bias representing binary 0.

The circuit of the article modified in the way shown in FIG. 4 is attractive for implementing the present invention as it readily may be integrated. MOreover, the circuit includes means for obtaining a normal output from the signal present at lead 40 and a complemented output from the signal present at lead 38 (across a resistor output is placed in its current path). Nevertheless, it is to'be understood that this is merely one example as it is possible to implement the circuit in may other ways.

What we claim is:

l. A storage circuit comprising, in combination:

a three-input AND gate;

three two-input OR gates, each connected at its output terminal to a different input terminal to said three-input gate;

a feedback connection from the output terminal of said three-input gate to the first and second of said two-input gates;

means for applying a control signal to the first two-input gates and its complement to the third two-input gate; and

means for applying an information signal to the second and third two-input gates.

2. A storage circuit as set forth in claim 1 wherein said three input AND gate has a second output terminal, this one for producing an output indicative of the NAND function.

3. A storage circuit comprising, in combination:

a three-input AND gate;

three two-input gates, each connected at its output terminal to a different input tenninal to said AND gate; and

a feedback connection from the output terminal of said AND gate solely to the first and second of said OR gates. 

1. A storage circuit comprising, in combination: a three-input AND gate; three two-input OR gates, each connected at its output terminal to a different input terminal to said three-input gate; a feedback connection from the output terminal of said threeinput gate to the first and second of said two-input gates; means for applying a control signal to the first two-input gate and its complement to the third two-input gate; and means for applying an information signal to the second and third two-input gates.
 2. A storage circuit as set forth in claim 1 wherein said three input AND gate has a second output terminal, this one for producing an output indicative of the NAND function.
 3. A storage circuit comprising, in combination: a three-input AND gate; three two-input OR gates, each connected at its output terminal to a different input terminal to said AND gate; and a feedback connection from the output terminal of said AND gate solely to the first and second of said OR gates. 